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| sames FEATURES n SA9203/5 6/3 X 8 PORT EXPANDER Six (SA9203) or three (SA9205) 8-Bit I/O Ports Each bit of one port independently programmable as input or output Five (SA9203) or two (SA9205) remaining ports can be individually configured as input or output. (Direction applicable to all 8 pins of each port.) One 8-Bit port programmable as either atched or transparent inputs Supports byte-wide and bit-wide I/O port addressing modes on all ports n Readback of all control and port registers Interfaces directly with multiplexed address and data bus microprocessors/ microcontrollers Internal address latch Single +5V power supply Low power CMOS Completely static operation TTL-level compatibility n n n n n n n n n n FIGURE 1: PIN CONNECTION FOR DESCRIPTION The SAMES SA9203/5 Port Expander is a SA9203 CMOS device suited to microprocessor based applications requiring input/output port expansion. The device interfaces very 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 simply to any microcontroller/micro60 PA 0 10 59 processor with a multiplexed address/data PA 1 11 58 PA 2 12 57 bus structure. PA 3 13 56 PA 4 14 55 The SA9203 includes 8 independently PA 5 15 54 PA 6 16 53 programmable I/O pins for Port A and Port PA 7 17 52 SA9203 V DD 18 B to F (5 ports) independently programmable 51 PB 0 19 50 PB 1 20 as I/O. It is packaged in a PCB efficient 68 49 PB 2 21 48 pin PLCC package. The SA9205 includes PB 3 22 47 PB 4 23 46 8 independently programmable I/O pins for PB 5 24 45 PB 6 25 44 Port A with Port B and Port C as indepenPB 7 26 dently programmable I/O, packaged in a 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 cost effective 44 pin PLCC package. STB RST INT WR RD ALE CS A8 V SS AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 PC 4 PC 5 PC 6 PC 7 V SS PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 DR-01266 PF 7 PF 6 PF 5 PF 4 PF 3 PF 2 PF 1 PF 0 V DD PE 7 PE 6 PE 5 PE 4 PE 3 PE 2 PE 1 PE 0 PC 0 PC 1 PC 2 PC 3 1/14 4491 PDS039-SA9203/5-001 REV. A 20-08-96 SA9203/5 FIGURE 2: BLOCK DIAGRAM FOR SA9203 STB ALE CS RD WR RST INT P Inter face POR A POR B POR C POR D POR E POR F PA(7: PB(7: PC(7: PD(7: PE(7: PF(7: CON PRTA CON PRTB AD(7:0 DR-01267 FIGURE 3: PIN CONNECTION FOR SA9205 AD 7 AD 6 AD 5 V SS AD 4 AD 1 41 6 5 4 3 2 1 44 AD 3 NC CS 43 AD 2 42 AD 0 40 ALE RD WR INT RST V DD STB PA 0 PA 1 PA 2 PA 3 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 PC 7 PC 6 PC 5 PC 4 PC 3 V DD PC 2 PC 1 PC 0 PB 7 PB 6 SA9205 34 33 32 31 30 29 PB 1 PB 2 PA 7 PB 0 V SS PA 4 PA 5 PB 3 DR-01268 2/14 sames PB 4 PB 5 PA6 SA9203/5 FIGURE 4: BLOCK DIAGRAM FOR SA9205 STB ALE CS RD WR RST INT P Interface CON PRTA PORT C PC(7:0) PORT B PB(7:0) PORT A PA(7:0) AD(7:0) CON. PRTBC DR-01269 ABSOLUTE MAXIMUM RATINGS* (All voltages are with respect to VSS) Parameter Supply Voltage Voltage on any pin Current at any pin Storage Temperature Operating Temperature Symbol VDD-VSS VM IM TSTG TO Min VSS VSS-0.3 -40 0 Max 7,0 V DD+0.3 100 +125 +70 Unit V V mA C C * Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other condition above those indicated in the operational sections of this specification, is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. sames 3/14 SA9203/5 ELECTRICAL CHARACTERISTICS (All measurements with respect to VSS, at 25C, unless otherwise specified) Parameters Supply Voltage Static Current Dynamic Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Tristate Leakage Current Note 1: Symbol V DD IDDS IDDD VIH VIL VOH VOL IIN ITL Min 4.75 Typ Max 5.0 5.25 15 50 20 2.0 1.0 4.5 4.7 0.25 0.5 <1.0 3.0 <1.0 3.0 Unit V A mA V V V V A A Condition VDD = 5.0V (See Note1) VDD = 5.0V VDD = 5.0V VDD = 5.0V VDD = 5.0V IOH = 5mA VDD = 5.0V IOH = 5mA VDD = 5.0V VDD = 5.0V All inputs tied to VDD or VSS with outputs not loaded. Measurements made after RST applied. 4/14 sames SA9203/5 PIN DESCRIPTION for SA9203 Pin Type Designation 18,52 VDD 1,35 VSS 61..68 I/O AD0..AD7 Description +5V Supply Input 0V ground Reference 3-state address/data lines that interface with the CPU lower 8-bit address/data bus. The 8-bit address is latched into the SA9203 internal address latch on the falling edge of ALE. The 8-bit data is respectively written into and read out of the SA9203 on WR and RD signals. Not connected. Active low input signal used to select the device. This control signal latches the address on the AD0..7 lines on the falling edge of ALE. Input low on this line enables the data bus buffers. Input low on this line causes the data on the address/ data bus to be written to the I/O ports and, control registers. If enabled via A.6, this output will be set (active edge polarity programmed by D6 and output polarity programmed via D7 of the Port B-F direction control register) after data has been latched into PORT A. Input low on this line resets the chip and all internal registers and all ports to input mode (The register contents after a reset pulse will be described later). Input data on PORT A pins will be latched when STB is active and transparent otherwise (polarity programmed by D5 of the Port B-F direction control register) 8 general purpose I/O pins comprising PORT A. This port supports individual input or latched output configuration of each pin. In addition,each pin of PORT A selected as an input can be programmed to be latched or transparent. 8 general purpose I/O pins comprising PORT B. All 8 pins are programmed to be either latched outputs or transparent inputs. Identical to PORT B Identical to PORT B Identical to PORT B Identical to PORT B 5/14 2 3 4 5 6 I I I I N/C CS ALE RD WR 7 O INT 8 I RST 9 I STB 10..17 I/O PA0..PA7 19..26 I/O PB0..PB7 27..34 36..43 44..51 53..60 I/O I/O I/O I/O PC0..PC7 PD0..PD7 PE0..PE7 PF0..PF7 sames SA9203/5 PIN DESCRIPTION for SA9205 Pin 2,35 1,23 40..44 Type Designation VDD VSS I/O AD0..AD7 Description +5V Supply Input 0V ground Reference 3-state address/data lines that interface with the CPU lower 8-bit address/data bus. The 8-bit address is latched into the SA9203 internal address latch on the falling edge of ALE. The 8-bit data is respectively written into and read out of the SA9203 on WR and RD signals. Not connected. Active low input signal used to select the device. This control signal latches the address on the AD0..7 lines on the falling edge of ALE. Input low on this line enables the data bus buffers. Input low on this line causes the data on the address/ data bus to be written to the I/O ports and, control registers. If enabled via A.6, this output will be set (active edge polarity programmed by D6 and output polarity programmed via D7 of the Port B-F direction control register) after data has been latched into PORT A. Input low on this line resets the chip and all internal registers and all ports to input mode (The register contents after a reset pulse will be described later). Input data on PORT A pins will be latched when STB is active and transparent otherwise (polarity programmed by D5 of the Port B-F direction control register) 8 general purpose I/O pins comprising PORT A. This port supports individual input or latched output configuration of each pin . In addition,each pin of PORT A selected as an input can be programmed to be latched or transparent. 8 general purpose I/O pins comprising PORT B. All 8 pins are programmed to be either latched outputs or transparent inputs. Identical to PORT B 5 6 7 8 9 I I I I N/C CS ALE RD WR 10 O INT 11 I RST 13 I STB 14..21 I/O PA0..PA7 22, 24.30 31..39 I/O PB0..PB7 I/O PC0..PC7 6/14 sames SA9203/5 FUNCTIONAL DESCRIPTION The SA9203 contains the following: * Six 8-bit general purpose I/O ports programmable to be either byte or bit addressable. * Two control registers for configuring the device. These control registers can be read back. * An internal address latch for accessing a multiplexed CPU address/data bus. * The SA9203 appears to the CPU as a peripheral device occupying 256 bytes of memory space. Certain locations in the memory map are occupied by the six I/O ports and two control registers. The SA9203 supports two basic I/O port addressing modes, via; byte-addressing and bit-addressing. Any of the six I/O ports can be configured as byte-addressable /or bitaddressable. In bit-addressing, individual bits of any I/O port can be addressed independently. In a bit- addressing CPU read operation, D0 contains valid data while D1..D7 should be ignored. In a bit-addressing CPU write operation, D0 will be written to the addressed output pin while D1..D7 will be ignored. The Address Memory map is shown in Figure 5. The bit-addressing mode applies to both the I/O ports and the control registers. The SA9205 is a three port device with operation is identical to the SA9203. FIGURE 5: Address Memory Map W A7 BM W W W W W W W A6 A5 A4 A3 A2 A1 A0 EI CR2 CR1 CR0 BM2 MB1 BM0 Bit mode address 0 Bit mode address 1 Bit mode address 2 Control register address 0 Control register address 1 Control register address 2 0: Interupt function disabled 1: Interupt function enabled 0: Bit mode addressing enabled 1: Byte mode addressing enabled 7/14 sames SA9203/5 FIGURE 6: PORT A Direction Control Register Address. A5 A4 A3 1 1 0 FIGURE 7: PORT B..F Direction Control Register / Strobe Control Register Address A5 A4 A3 1 1 1 FIGURE 8: PORT Addresses A5 A4 A3 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 PORT PORT A PORT B PORT C PORT D * PORT E * PORT F * * - n/a for the SA9205 FIGURE 9: Port Pin Addresses (Bit Mode Only). A2 A1 A0 PORT PIN 0 0 0 PORT A-F.0 0 0 1 PORT A-F.1 0 1 0 PORT A-F.2 0 1 1 PORT A-F.3 1 0 0 PORT A-F.4 1 0 1 PORT A-F.5 1 1 0 PORT A-F.6 1 1 1 PORT A-F.7 Note : PORT A-C for SA9205 CONTROL REGISTERS FIGURE 10: PORT A Direction Control Register R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 PA.7 PA.6 PA.5 PA.4 PA.3 PA.2 D = 1 Port A Pin configured as output D = 0 Port A Pin configured as input. sames R/W D1 PA.1 R/W D0 PA.0 8/14 SA9203/5 FIGURE 11: PORT B-F Direction Control / Strobe Control Register Address R/W R/W R/W R/W R/W R/W R/W R/W D7 D6 D5 D4 D3 D2 D1 D0 IP IE SP DF* DE* DD* DC DB 0: PORT B Configured as input 1: PORT B Configured as output 0: PORT C Configured as input 1: PORT C Configured as output 0: PORT D Configured as input 1: PORT D Configured as output 0: PORT E Configured as input 1: PORT E Configured as output 0: PORT F Configured as input 1: PORT F Configured as output 0: PORT A data latched when STB low and transparent when STB high. 1 - Port A data latched when STB high and transparent when STB low. 0 - Interupt output (INT) set on the rising edge of STB. 1 - Interupt output (INT) set on the falling edge of STB. 0: Interupt output active High 1: Interupt output active low * n/a for the SA9205 sames 9/14 SA9203/5 INT This active high output (default after reset) operates as follows: When disabled (via A6), INT remains reset. On either the rising or trailing edge of STB (programmable via D6 of Port B-F direction control register), INT is set. INT remains set until Port A (or any bit of PORT A if in bit- addressing mode) is read by the microprocessor at which point INT is reset, remaining so until the next active edge of STB. (See figure 14 for timing diagram). The output polarity of INT is programmed via D7 of the Port B- F dirction control register (See Figure 11). RST This active low reset signal resets the contents of all registers to zero. Sets all ports to input mode and the bi-directional data/address bus to input. A valid RST signal is specified as an active low pulse of 100ns minimum duration. CS The active low CS signal is internally latched by the trailing edge of ALE. TIMING DIAGRAMS FIGURE 12: P Read Waveforms CS t AD AD 0-8/A 8 ADDRESS t AL ALE t LL RD t RDE t RD t LC t LD DR-01270 DATA VALID t LA t RDF t CC t CL t RV 10/14 sames SA9203/5 FIGURE 13: P Write Waveforms CS AD 0 -8/A 8 ADDRESS t AL t LA DATA VALID t DW t CL ALE t LL WR DR-01271 t LC t WD t RV t WT t CLL t CC FIGURE 14: P Strobe/Interrupt Waveforms STB OR* STB t SS INT or INT t PSS t PHS INPUT DATA FROM PORTA * DEPENDENT ON SP # DEPENDENT ON IP DR-01272 t SI t RDI sames 11/14 SA9203/5 FIGURE 15: I/O Port Waveforms Transparent Output t RP RD INPUT t PR DATA BUS * X DATA VALID DR 01273 FIGURE 16: P Read Waveforms Latched Output WR DATA BUS * DATA VALID t WP X X OUTPUT DR-01274 Table 1: AC Characteristics for P Interface1 - TA = 0C to 70C, VDD = 5V 10% Symbol tAL tLA tLC tRD tLD tAD tLL tRDF tCL tCLL tCC tDW tWD tRV tRDE 12/14 Parameter Address to Latch Setup Time Address Hold Time after Latch Latch to READ/WRITE Control Valid Data Out Delay from READ Control Latch to Data Out Valid Address Stable to Data Out Valid Latch Enable Width Data Bus Float after READ READ/WRITE Control to Latch Enable WRITE Control to Latch Enable READ/WRITE Control Width Data in to WRITE Setup Time Data in Hold Time after WRITE Recovery Time between READ/WRITE Data Bus Enable from READ Control sames Min 10 10 10 Max 50 50 100 30 0 10 50 60 20 20 50 10 40 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SA9203/5 Table 2: A.C. Characteristics for I/O Ports Symbol tPR tRP tSS tSI tRD tPSS tPHS tWP Parameter Port Input Setup Time Port Input Hold Time Strobe Width Strobe to INT Set READ to INT Reset Port Setup Time to Strobe Port Hold Time After Strobe WRITE to Port Output Min 20 0 100 Max Units ns ns ns ns ns ns ns ns 100 100 50 120 80 Note 1: Timing parameters are preliminary and subject to change. sames 13/14 SA9203/5 Disclaimer: The information contained in this document is confidential and proprietary to South African MicroElectronic Systems (Pty) Ltd ("SAMES) and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of SAMES. The information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to inform any recipient of this document of any changes in the information contained herein, and SAMES expressly reserves the right to make changes in such information, without notification,even if such changes would render information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer. South African Micro-Electronic Systems (Pty) Ltd P O Box 15888, 33 Eland Street, Lynn East, Koedoespoort Industrial Area, 0039 Pretoria, Republic of South Africa, Republic of South Africa Tel: Fax: 14/14 012 333-6021 012 333-8071 sames Tel: Fax: Int +27 12 333-6021 Int +27 12 333-8071 |
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